Skip to content

ISUB_R fix for ARM/RISC-V JIT (master)#326

Merged
SChernykh merged 2 commits into
tevador:masterfrom
SChernykh:isub_r_fix_master
May 9, 2026
Merged

ISUB_R fix for ARM/RISC-V JIT (master)#326
SChernykh merged 2 commits into
tevador:masterfrom
SChernykh:isub_r_fix_master

Conversation

@SChernykh
Copy link
Copy Markdown
Collaborator

See #325

@SChernykh SChernykh requested a review from tevador May 9, 2026 09:22
@SChernykh SChernykh requested a review from hyc May 9, 2026 09:37
@SChernykh SChernykh merged commit 0dea273 into tevador:master May 9, 2026
18 checks passed
SChernykh added a commit to SChernykh/RandomX that referenced this pull request May 10, 2026
When `src = dst` and `imm = 0x80000000` in ISUB_R, the JIT generated the wrong code because negating 0x80000000 (-2^31) resulted in -2^31 again, not +2^31.

Also added the test to `tests.cpp` to check this case (can be verified by disabling the fix in jit_compiler_a64/jit_compiler_rv64).
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

2 participants