Complete 2.4 GHz RF receiver front-end designed in Cadence Virtuoso (180 nm CMOS) — cascode LNA, Gilbert cell mixer, and Gm-C IF filter. Serving as the analog verification layer for a 64 subcarrier OFDM PHY baseband. Simulated in Spectre RF.

A SSI Digital IC based on 180nm technology that will give us outputs of all the Logic gates.

This is the Repository which contains the detail of my work done at SCL Mohali (formerly Department of Space, ISRO). This was the internship basically focused on the "Experimental Analysis of MOS Capacitor for Oxide Furnaces" and further study of VLSI.