SystemVerilog implementation of RISC-V RV32I_Zmmul & custom packed SIMD ISA as 5-stage single-issue CPU core with branch predictor and L1 caches, tied up in lockstep with ISA sim over DPI for verification
C++ Instruction Set Simulator for RISC-V RV32IMC & custom packed SIMD ISA with cache and branch predictor models, C/ASM workloads, and Python analysis tools
An 8-bit CPU with a custom ISA, designed from scratch in Verilog, and its complete assembler toolchain developed in C++.
⛵️ A statically-typed, compiled programming language targeting a custom 16-bit ARM-like CPU architecture.
Emulator for Computer Organization Course Mini Project
Assember for Computer Organization Course Mini Project
A custom 16-bit MIPS-inspired processor built in Logisim, featuring a unique instruction set, ALU, register file, and memory components. Designed for educational purposes and low-level computing exploration.
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