Data structure I BRAC University's course - CSE220-Lab Assignment Solutions. (Spring-2026)
In CSE332L: Computer Organization and Architecture Lab, I completed an assignment involving several Verilog tasks, where I solved the problems using behavioral, dataflow, and gate-level modeling.
I have built a R-type and I-type datapath for a 16-bit system in logisim, featuring 16 bit data, 4-bit addressing (16 registers) and 16-bit instructions, where the ALU is capable of performing 8 operations. More descriptions are written inside the file
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