This work presents the design and implementation of high performance and low power 32-bit RISC-V processor 4-stage pipelined for non-load and 5-stage for load operations, also extending its capabilities as system on chip (SoC) design. RV32I with M extension designed for FPGA and ASIC

SystemVerilog implementation of a Binary to Gray Code Converter in both structural and behavioral styles. Includes a simple testbench for verification. Useful for digital design learners and FPGA developers.

Quantum Key Distribution (QKD) Post-Processing: C++ simulation of sifting & error correction, and Verilog HDL implementation of hardware-optimized sifting and privacy amplification using NTT-based architecture. Includes testbenches, results, and FPGA validation.