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@ZhaoxiangJin ZhaoxiangJin commented Dec 13, 2025

  1. This PR refactors the mcux sar adc driver. Zephyr's current ADC API only supports 32 logical channels, which is inadequate for SAR ADCs on certain SoCs. For instance, the ADC on the MCXE31B has 64 hardware channels. The previous implementation used a one-to-one mapping between logical and hardware channels. In the new SAR ADC driver version, we bind hardware channels to logical channels via the zephyr,input-positive property, enabling us to access any channel. Currently, only imx93 uses this ADC. To maintain the bisectability of Zephyr commits, the refactored code and imx93-related file updates are placed in the same commit. The migration-guide-4.4.rst has also been updated accordingly to document this change.
  2. Now the sar adc is native driver, so, remove CONFIG_MCUX_COMPONENT_driver.sar_adc from the glue cmake.
  3. Enabled sar adc for mcxe31b platform.
  4. Enabled adc samples for frdm-mcxe31b.
Logs
*** Booting Zephyr OS build v4.3.0-2350-gbbff45f1c4cf ***
ADC reading[0]:
- adc@a0000, channel 24: 11754 = 1183 mV
- adc@a0000, channel 31: 32216 = 3244 mV
ADC reading[1]:
- adc@a0000, channel 24: 11738 = 1182 mV
- adc@a0000, channel 31: 32208 = 3243 mV
ADC reading[2]:
- adc@a0000, channel 24: 11754 = 1183 mV
- adc@a0000, channel 31: 32216 = 3244 mV
ADC reading[3]:
- adc@a0000, channel 24: 11738 = 1182 mV
- adc@a0000, channel 31: 32208 = 3243 mV
*** Booting Zephyr OS build v4.3.0-2350-gbbff45f1c4cf ***
ADC sequence reading [0]:
- adc@a0000, channel 24, 5 sequence samples:
- - 11674 = 1175mV
- - 11962 = 1204mV
- - 11946 = 1203mV
- - 11938 = 1202mV
- - 11922 = 1200mV
- adc@a0000, channel 31, 5 sequence samples:
- - 32208 = 3243mV
- - 32216 = 3244mV
- - 32208 = 3243mV
- - 32208 = 3243mV
- - 32208 = 3243mV
ADC sequence reading [1]:
- adc@a0000, channel 24, 5 sequence samples:
- - 11738 = 1182mV
- - 11938 = 1202mV
- - 11962 = 1204mV
- - 11962 = 1204mV
- - 11930 = 1201mV
- adc@a0000, channel 31, 5 sequence samples:
- - 32208 = 3243mV
- - 32208 = 3243mV
- - 32208 = 3243mV
- - 32208 = 3243mV
- - 32208 = 3243mV
ADC sequence reading [2]:
- adc@a0000, channel 24, 5 sequence samples:
- - 11738 = 1182mV
- - 11938 = 1202mV
- - 11922 = 1200mV
- - 11938 = 1202mV
- - 11962 = 1204mV
- adc@a0000, channel 31, 5 sequence samples:
- - 32208 = 3243mV
- - 32216 = 3244mV
- - 32208 = 3243mV
- - 32208 = 3243mV
- - 32208 = 3243mV

@ZhaoxiangJin ZhaoxiangJin changed the title Rewrite sar adc driver refactors the mcux sar adc driver Dec 13, 2025
@ZhaoxiangJin ZhaoxiangJin changed the title refactors the mcux sar adc driver refactors mcux sar adc driver Dec 13, 2025
@ZhaoxiangJin ZhaoxiangJin force-pushed the rewrite-sar-adc-driver branch 4 times, most recently from 850d1c3 to a469029 Compare December 14, 2025 12:41
@ZhaoxiangJin ZhaoxiangJin changed the title refactors mcux sar adc driver refactor mcux sar adc driver Dec 14, 2025
@ZhaoxiangJin ZhaoxiangJin marked this pull request as ready for review December 15, 2025 01:35
@ZhaoxiangJin ZhaoxiangJin force-pushed the rewrite-sar-adc-driver branch from a469029 to c908ef4 Compare December 15, 2025 07:52
@zephyrbot zephyrbot added area: ADC Analog-to-Digital Converter (ADC) area: Samples Samples Release Notes To be mentioned in the release notes platform: NXP MCU labels Dec 15, 2025
@ZhaoxiangJin ZhaoxiangJin force-pushed the rewrite-sar-adc-driver branch 2 times, most recently from cc215e1 to c10c8e8 Compare December 16, 2025 01:52
Zephyr's current ADC API only supports 32 logical channels,
which is inadequate for SAR ADCs on certain SoCs. For instance,
the ADC on the MCXE31B has 64 hardware channels. The previous
implementation used a one-to-one mapping between logical and
hardware channels. In the new SAR ADC driver version, we bind
hardware channels to logical channels via the zephyr,input-positive
property, enabling us to access any channel.

Currently, only imx93 uses this ADC. To maintain the bisectability
of Zephyr commits, in this commit we will also modify the imx93-related
files.

Now the sar adc is native driver, so, remove
CONFIG_MCUX_COMPONENT_driver.sar_adc from the glue cmake.

Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
enable ADC clock control

Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Enable SAR ADC support for frdm_mcxe31b.

Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Enable adc_sequence and adc_dt samples on frdm_mcxe31b board

Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add migration guide documentation for NXP SAR ADC driver.

Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
@ZhaoxiangJin ZhaoxiangJin force-pushed the rewrite-sar-adc-driver branch from c10c8e8 to be0bd7b Compare December 16, 2025 02:31
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area: ADC Analog-to-Digital Converter (ADC) area: Boards/SoCs area: Clock Control area: Devicetree Bindings area: Samples Samples area: Tests Issues related to a particular existing or missing test platform: NXP MCU platform: NXP NXP Release Notes To be mentioned in the release notes

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