feat(designs): add PE_INT implementation flow

[HLEE80]

Summary

• Add the PE_INT PyCircuit design flow, generated RTL, model, and RTL/PyCircuit test environments.
• Strengthen PE_INT verification with exact L=4 scoreboards, random-valid timing cases, public PyCircuit API usage, and generated RTL warning cleanup.
• Add PE_INT flow guardrails, regression evidence, circuit optimizer documentation, and project-level codereviewer configuration.

Test plan

• PASS: python3 model/test_pe_int.py under WSL with PE_INT/PyCircuit PYTHONPATH.
• PASS: python3 python/build.py --target both --out-dir build/pe_int --jobs 8 --pyc-tb-vectors 8 under WSL.
• PASS: ./build/pe_int/cpp_build/build/pyc_tb.
• PASS: bash sim/run_all_wsl.sh covering 9 RTL cases with both iverilog and verilator -Wall.
• PASS: Pre-PR codereviewer gate returned PASS_WITH_NOTES; notes are limited to accepted rst_n framework limitation and deferred Booth topology pending synthesis evidence.

Notes

• rst_n async assertion / sync release mismatch is tracked as a known PyCircuit framework limitation.
• Explicit radix-4 Booth multiplier topology remains documented as deferred until synthesis/timing/area evidence is available.

[gemini-code-assist]

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