AI-powered hardware development platform — design, verify, synthesize, and deploy working RTL with natural language. Supports SystemVerilog, Verilog, and VHDL across the full open-source FPGA toolchain.
Loving hardware doesn't have to be gatekept.
GateFlow brings professional hardware development tooling to Claude Code. Describe what you want to build — including your target board — and get lint-checked, simulated, formally verified, synthesis-ready code with correct pin assignments.
Whether you're writing your first always_ff, formally proving your FIFO never overflows, or synthesizing an SPI controller for your Arty A7, the tools should help you, not fight you.
We can't wait to see what you create. ❤️
- Quick Start — Install in one command
- Usage — Natural language, skills, and commands
- Features — What makes GateFlow different
- Components — All skills, agents, and commands
- Individual Downloads — Grab single components
- Cross-Tool Compatibility — Use with Codex, Cursor, Copilot, Cline, Windsurf
- Configuration — Project-specific settings
- Project Structure — Repo layout
- Troubleshooting — Common issues
- Updates — Changelog
- Releases — Detailed release notes
- Contributing | License | Links
# Option 1: Marketplace (recommended)
claude plugin marketplace add codejunkie99/Gateflow-Plugin
claude plugin install gateflow
# Option 2: Clone and run
git clone https://github.com/codejunkie99/Gateflow-Plugin.git
claude --plugin-dir ./Gateflow-Plugin/plugins/gateflow
# Option 3: Persistent (add to ~/.claude/settings.json)
git clone https://github.com/codejunkie99/Gateflow-Plugin.git ~/.claude-plugins/gateflow-marketplaceFor Option 3, add to ~/.claude/settings.json or .claude/settings.json:
{
"plugins": [
"~/.claude-plugins/gateflow-marketplace/plugins/gateflow"
]
}| Tool | Required | macOS | Linux |
|---|---|---|---|
| Claude Code | Yes | See website | See website |
| Verilator | Recommended | brew install verilator |
sudo apt install verilator |
| Verible | Optional | brew tap chipsalliance/verible && brew install verible |
See releases |
| Yosys | For synthesis | brew install yosys |
sudo apt install yosys |
| SymbiYosys | For formal | pip install symbiyosys |
pip install symbiyosys |
| GHDL | For VHDL | brew install ghdl |
sudo apt install ghdl |
| nextpnr | For P&R | brew install nextpnr |
See GitHub |
| openFPGALoader | For flash | brew install openfpgaloader |
See GitHub |
# Verify installation
/gf-doctor
# Update (marketplace)
# /plugin → Marketplaces → gateflow → Update → restart Claude Code
# Update (local)
# git pull in your plugin folder, then restart Claude CodeGateFlow understands context. Describe what you need in plain English:
"Create a FIFO and test it"
→ Generates FIFO, creates testbench, runs simulation, fixes issues, delivers working code
"Formally verify that the FIFO never overflows"
→ Generates SVA properties, configures SymbiYosys, runs proof, reports results
"Synthesize my design for the iCEBreaker board"
→ Runs Yosys synthesis, reports LUT/FF/BRAM usage, generates constraint file
"Add an SPI controller to my project"
→ Installs verified SPI master IP block with testbench and formal proofs
"What pins does the Arty A7 PMOD JA have?"
→ Looks up curated board database, shows pin assignments with I/O standards
"Why is my output X?"
→ Analyzes code, traces signal path, identifies root cause
"Plan a DMA controller"
→ Creates detailed design plan with block diagrams, FSMs, interfaces, verification strategy
Skills activate automatically based on context:
| Skill | Trigger | What It Does |
|---|---|---|
/gf |
Any SV task | Main orchestrator — plan-first, parallel build, verify until working |
/gf-plan |
"plan", "design", "architect" | RTL implementation plans with ASCII diagrams |
/gf-build |
"build", "multi-component", "SoC" | Parallel component build orchestration |
/gf-formal |
"formally verify", "prove", "check property" | Formal verification from natural language via SymbiYosys |
/gf-synth |
"synthesize", "area estimate", "resource usage" | Yosys synthesis with LUT/FF/BRAM/DSP reports |
/gf-architect |
"map codebase", "analyze project" | Codebase map with hierarchy, FSMs, clocks, CDC |
/gf-viz |
"visualize", "show hierarchy" | Terminal ASCII visualization of RTL architecture |
/gf-learn |
"teach me", "exercise", "practice" | Learning mode with exercises and feedback |
| Command | What It Does |
|---|---|
/gf-lint |
Run Verilator lint with structured output |
/gf-fix |
Auto-fix lint errors |
/gf-sim |
Compile and run simulation |
/gf-formal |
Run SymbiYosys formal verification |
/gf-gen |
Generate module/testbench scaffolds |
/gf-ip |
Manage verified IP block library (add/list/info) |
/gf-boards |
List supported FPGA boards and query pinouts |
/gf-demo |
One-command zero-config showcase project |
/gf-scan |
Index project files |
/gf-map |
Map codebase architecture |
/gf-doctor |
Check environment and dependencies |
$ claude --plugin-dir ./Gateflow-Plugin/plugins/gateflow
You: Create a parameterized counter with enable and test it
Claude: Creating counter module...
✓ Created counter.sv
Running lint check...
✓ Lint clean
Creating testbench...
✓ Created tb_counter.sv
Running simulation...
✓ All tests pass (12 checks)
Done! Created:
- rtl/counter.sv (8-bit parameterized counter with enable)
- tb/tb_counter.sv (Self-checking testbench)
The /gf orchestrator doesn't stop at generation — it verifies:
Create → Lint → Fix → Test → Fix → Formally Verify → Synthesize → Deliver
Tell GateFlow what to prove in plain English:
"Formally verify that the FIFO never overflows and the pointers are always consistent"
→ Generates SVA assert property statements
→ Configures SymbiYosys (.sby file)
→ Runs bounded model checking
→ Reports proof results or explains counterexamples in English
"Synthesize my design for the iCEBreaker"
→ Checks for unsupported SV constructs (warns before failing)
→ Runs Yosys synthesis targeting iCE40
→ Reports: LUTs: 142, FFs: 87, BRAM: 1, DSP: 0
8 verified, formally proven IP blocks ready to use:
/gf-ip add fifo_sync → Installs FIFO with RTL + testbench + formal proofs
/gf-ip add uart → UART TX+RX with configurable baud rate
/gf-ip add axi4lite_slave → AXI4-Lite register interface
Every block is lint-clean, simulation-tested, and formally verified.
GateFlow knows your FPGA board's pinout:
/gf-boards arty-a7-35t pmod-ja → Shows exact pin assignments
Curated constraint files (.xdc, .pcf, .cst) for popular boards included.
/gf-plan creates professional design documents:
- Block diagrams (ASCII and Mermaid)
- Module hierarchy and interface specs
- FSM state diagrams
- Clock domain analysis
- Verification strategy and implementation phases
/gf-architect maps your entire project:
- Module hierarchy and dependencies
- Signal flow analysis and FSM extraction
- Clock domain crossing detection
- Package and type definitions
- Memory: FIFOs, dual-port RAM, register files
- Error handling: ECC, watchdogs, TMR
- DFT: Scan chains, JTAG, BIST
- Timing: Retiming, pipelining, SDC
- Verification: SVA, coverage, formal
GateFlow watches your workflow and helps proactively:
- After SV edits — reminds you to lint
- Before destructive commands — warns if you're about to delete SV files
- On session end — checks if you forgot to lint or simulate modified files
- Progressive tips — surfaces slash commands you haven't used yet
| Skill | Description | Source |
|---|---|---|
gf |
Main orchestrator — plan, build, verify until working | SKILL.md |
gf-plan |
RTL implementation planning with diagrams | SKILL.md |
gf-build |
Parallel component build orchestration | SKILL.md |
gf-formal |
Formal verification from natural language (SymbiYosys) | SKILL.md |
gf-synth |
Yosys synthesis with area/timing reports | SKILL.md |
gf-ip |
IP block library — verified drop-in components | SKILL.md |
gf-architect |
Codebase map with hierarchy, FSMs, clocks, CDC | SKILL.md |
gf-lint |
Structured Verilator lint checking | SKILL.md |
gf-sim |
Simulation with auto DUT/TB detection | SKILL.md |
gf-viz |
Terminal visualization of RTL architecture | SKILL.md |
gf-learn |
Learning mode — exercises, reviews, hints | SKILL.md |
gf-errors |
3-layer error translation for hardware tools | SKILL.md |
gf-project |
Project context (.gateflow/project.yaml) management | SKILL.md |
gf-router |
Intent classification and routing | SKILL.md |
gf-expand |
Clarifying questions with trade-offs | SKILL.md |
gf-summary |
Summarize Verilator/lint output | SKILL.md |
tb-best-practices |
Testbench best practices reference | SKILL.md |
gf-pinmap |
Board-aware pin mapping with constraint generation | SKILL.md |
gf-pnr |
Place & route via nextpnr (iCE40/ECP5/Gowin) | SKILL.md |
gf-protocols |
Protocol scaffolding (AXI4, SPI, I2C, Wishbone) | SKILL.md |
gf-pcb |
KiCad schematic/PCB with AI verification loop | SKILL.md |
gf-cocotb |
Python testbenches via Cocotb | SKILL.md |
gf-fusesoc |
FuseSoC build system integration | SKILL.md |
gf-learn-ctx |
Contextual learning — micro-lessons in workflows | SKILL.md |
gf-ip-detect |
Auto-detect IP blocks — scan, match, auto-fill gaps | SKILL.md |
| Agent | Expertise | Source |
|---|---|---|
sv-codegen |
RTL architect — synthesizable modules | sv-codegen.md |
sv-testbench |
Verification engineer — testbenches and stimulus | sv-testbench.md |
sv-debug |
Debug specialist — simulation failures, X-values | sv-debug.md |
sv-formal |
Formal verification — SVA properties, SymbiYosys proofs | sv-formal.md |
sv-synth |
Synthesis specialist — Yosys, area/timing optimization | sv-synth.md |
sv-verification |
Verification methodologist — SVA, coverage, formal | sv-verification.md |
sv-understanding |
RTL analyst — explains and documents code | sv-understanding.md |
sv-planner |
Architecture planner — design plans and diagrams | sv-planner.md |
sv-orchestrator |
Parallel builder — multi-component designs | sv-orchestrator.md |
sv-refactor |
Code quality — lint fixes, cleanup, optimization | sv-refactor.md |
sv-developer |
Full-stack RTL — complex multi-file features | sv-developer.md |
sv-tutor |
Teacher — reviews solutions, gives hints | sv-tutor.md |
sv-viz |
Terminal visualization of RTL architecture | sv-viz.md |
sv-pinmap |
Pin assignment specialist — constraint files | sv-pinmap.md |
vhdl-codegen |
VHDL code generation — entities and architectures | vhdl-codegen.md |
vhdl-testbench |
VHDL testbench — GHDL-compatible verification | vhdl-testbench.md |
pcb-designer |
KiCad PCB — AI-verified schematics and layouts | pcb-designer.md |
sv-ip-scanner |
IP scanner — detect missing modules, auto-fill | sv-ip-scanner.md |
| Command | Description | Source |
|---|---|---|
/gf-doctor |
Environment check | gf-doctor.md |
/gf-demo |
Zero-config showcase project | gf-demo.md |
/gf-formal |
Run formal verification | gf-formal.md |
/gf-ip |
Manage IP block library | gf-ip.md |
/gf-boards |
List boards and query pinouts | gf-boards.md |
/gf-scan |
Index project | gf-scan.md |
/gf-map |
Map codebase | gf-map.md |
/gf-lint |
Run lint | gf-lint.md |
/gf-fix |
Fix lint | gf-fix.md |
/gf-gen |
Generate scaffolds | gf-gen.md |
/gf-sim |
Run simulation | gf-sim.md |
/gf-pnr |
Place & route (nextpnr) | gf-pnr.md |
/gf-flash |
Flash FPGA board | gf-flash.md |
/gf-detect |
Scan for missing IP blocks and CDC issues | gf-detect.md |
/gf-pcb |
Generate KiCad schematic/PCB (AI-verified) | gf-pcb.md |
/gf-pinmap |
Generate pin constraint file for board | gf-pinmap.md |
/gf-cocotb |
Generate Python testbench (Cocotb) | gf-cocotb.md |
/gf-fusesoc |
Generate FuseSoC .core file | gf-fusesoc.md |
| Block | Description | Includes |
|---|---|---|
fifo_sync |
Synchronous FIFO (parameterized width/depth) | RTL + TB + formal |
fifo_async |
Async FIFO with Gray code pointers (CDC) | RTL + TB + formal |
cdc_2ff |
2-flip-flop synchronizer | RTL + TB + formal |
cdc_handshake |
Multi-bit handshake synchronizer | RTL + TB + formal |
uart |
UART TX+RX with configurable baud | RTL + TB + formal |
spi_master |
SPI master (all 4 CPOL/CPHA modes) | RTL + TB + formal |
axi4lite_slave |
AXI4-Lite register slave | RTL + TB + formal |
debouncer |
Button debouncer with edge detection | RTL + TB + formal |
Install with: /gf-ip add fifo_sync or "add a FIFO to my project"
| Board | FPGA | Toolchain |
|---|---|---|
| Digilent Arty A7-35T | Xilinx xc7a35t | Vivado / Yosys |
| Digilent Basys 3 | Xilinx xc7a35t | Vivado / Yosys |
| 1BitSquared iCEBreaker | Lattice iCE40UP5K | Yosys + nextpnr |
| Sipeed Tang Nano 9K | Gowin GW1NR-9 | Yosys + nextpnr |
Query with: /gf-boards arty-a7-35t or "what pins does the Arty A7 have?"
Agents are automatically invoked by /gf based on your request — you don't need to call them directly.
Don't need the full plugin? Grab individual components.
How to download single components
Each component is a standalone .md file. Download and drop into your plugin directory:
your-plugin/
├── .claude-plugin/
│ └── plugin.json
├── agents/ ← agent .md files
├── commands/ ← command .md files
└── skills/
└── skill-name/ ← SKILL.md files
└── SKILL.md
# Download an agent
curl -O https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/agents/sv-codegen.md
# Download a skill
mkdir -p skills/gf-plan
curl -o skills/gf-plan/SKILL.md https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/skills/gf-plan/SKILL.md
# Download a command
curl -O https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/commands/gf-lint.mdNote: Some skills (like
gf-plan) include reference files in areferences/subdirectory. For full functionality, download the entire skill folder.
GateFlow's skills and agents are plain Markdown — they work across AI coding tools.
Setup instructions for Codex, Cursor, Copilot, Cline, Windsurf
Codex uses the same SKILL.md format:
# User-global
mkdir -p ~/.codex/skills/gf-plan
curl -o ~/.codex/skills/gf-plan/SKILL.md \
https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/skills/gf-plan/SKILL.md
# Repo-level
mkdir -p .agents/skills/gf-lint
curl -o .agents/skills/gf-lint/SKILL.md \
https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/skills/gf-lint/SKILL.md| Location | Scope |
|---|---|
.agents/skills/ |
Current repo |
~/.codex/skills/ |
User-global |
/etc/codex/skills/ |
System-wide |
# Append to .cursorrules
curl -s https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/agents/sv-codegen.md \
>> .cursorrules
# Or: Settings → Agent Modes → Add Custom Mode → paste agent contentmkdir -p .github
curl -s https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/agents/sv-codegen.md \
>> .github/copilot-instructions.mdcurl -s https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/agents/sv-codegen.md \
>> .clinerules# As a rule
mkdir -p .windsurf/rules
curl -o .windsurf/rules/sv-codegen.md \
https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/agents/sv-codegen.md
# As a workflow
mkdir -p .windsurf/workflows
curl -o .windsurf/workflows/gf-plan.md \
https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/skills/gf-plan/SKILL.mdOpenCode supports MCP servers and skill files:
# Add GateFlow skills to your OpenCode config
mkdir -p .opencode/skills/gf-plan
curl -o .opencode/skills/gf-plan/SKILL.md \
https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/skills/gf-plan/SKILL.md
# Add agent definitions
curl -O https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/agents/sv-codegen.md| Tool | Where to Put Files | Format |
|---|---|---|
| Claude Code | Plugin skills/, agents/, commands/ |
Native |
| Codex CLI | ~/.codex/skills/ or .agents/skills/ |
SKILL.md |
| Cursor | .cursorrules or custom agent mode |
Append |
| Copilot CLI | .github/copilot-instructions.md |
Append |
| Cline | .clinerules |
Append |
| Windsurf | .windsurf/rules/ or .windsurf/workflows/ |
Individual .md |
| OpenCode | .opencode/skills/ or MCP |
SKILL.md / Agent .md |
Create .claude/gateflow.local.md in your project for project-specific settings:
---
verilator_flags: ["-Wall", "-Wno-UNUSED"]
top_module: chip_top
clock_freq: 100MHz
---
# Project Notes
- Memory mapped registers at 0x1000
- AXI4-Lite interface for configGateflow-Plugin/
├── plugins/gateflow/ # Main plugin source
│ ├── .claude-plugin/ # Plugin manifest
│ ├── agents/ # 18 specialized AI agents
│ ├── commands/ # 18 slash commands
│ ├── skills/ # 26 auto-activating skills
│ ├── hooks/ # Automation hooks + session tracking
│ ├── boards/ # Curated FPGA board database (4 boards)
│ ├── ip/ # Verified IP block library (8 blocks)
│ └── CLAUDE.md # SystemVerilog reference
├── agents/ # Mirrored agent entrypoints (symlinks)
├── skills/ # Mirrored skill entrypoints (symlinks)
├── docs/ # Compressed docs index
├── CLAUDE.md # SV reference (repo-level)
└── AGENTS.md # Docs index for non-Claude agents
| File | For |
|---|---|
CLAUDE.md |
Claude Code (primary reference) |
AGENTS.md |
Other AI agents (Cursor, Copilot, etc.) |
"Verilator not found"
verilator --version # Check if installed
brew install verilator # macOS
sudo apt install verilator # Linux (Debian/Ubuntu)"Plugin not loading"
claude --plugin-dir /path/to/Gateflow-Plugin/plugins/gateflow
ls /path/to/Gateflow-Plugin/plugins/gateflow/.claude-plugin/plugin.json"Agent not found"
Use the gateflow: prefix when spawning agents manually:
gateflow:sv-codegen
gateflow:sv-testbench
For detailed release notes, see releases.md.
| Version | Date | What Changed |
|---|---|---|
| 1.6.0 | 2026-03-26 | Version sync across plugin.json and marketplace.json; BSL-1.1 license confirmed |
| 1.5.3 | 2026-02-18 | Replace prompt-based PostToolUse hook with deterministic Python script |
| 1.5.2 | 2026-02-15 | Fix Stop hook JSON validation: replace prompt hook with deterministic command hook (non-blocking reminder) |
| 1.5.0 | 2025-02-11 | Terminal visualization with /gf-viz skill and sv-viz agent |
| 1.4.4 | 2025-02-11 | Individual component downloads, cross-tool install instructions |
| 1.4.3 | 2025-02-10 | Split gf-plan references, validation fixes, docs improvements |
Contributions welcome! Areas we'd love help with:
- Board definitions: Add your FPGA board to
plugins/gateflow/boards/ - IP blocks: Submit verified blocks to
plugins/gateflow/ip/ - Protocol support: AXI4-Full, PCIe, USB, Ethernet, Wishbone
- Tool integrations: Cocotb, FuseSoC, Edalize
- Documentation and examples
BSL-1.1 (Business Source License) — see LICENSE for details.
You can: Use, fork, contribute for non-commercial/personal/educational purposes. Commercial use: Contact us for a license. After 2028: Converts to Apache 2.0.
Built for hardware engineers who want to move faster.
Design. Verify. Ship.