v2.4.0 — Deep Skill Enrichment

The biggest content update in GateFlow history. Every skill in the plugin enriched with research-backed reference material.

By the numbers

• 37 files changed, +3,139 lines added
• 22 skills enriched (7 stub skills transformed, 15 existing skills deepened)
• 6 critical fixes applied
• 5 research agents gathered domain-specific content across formal verification, PCB design, FPGA toolchains, hardware AI landscape, and verification methodology

Highlights

Formal verification got real. gf-formal now has SymbiYosys .sby templates, 7 SVA property patterns, proof strategy decision trees, engine comparisons, and counterexample interpretation guides.

Protocols got scaffold code. gf-protocols went from an empty stub to actual AXI4-Lite, SPI, UART, and I2C module skeletons with integration examples.

Every skill returns structured data. All skills now have GATEFLOW-RESULT blocks so the orchestrator can parse them programmatically.

The orchestrator got smarter. Context-dependent routing, multi-intent detection, adaptive confidence calibration, and a 20-pattern error translation dictionary for Verilator/Yosys.

Learning mode leveled up. 5 new exercise topics, difficulty scaling, grading rubrics, challenge mode with timed scoring, and 15 new contextual micro-lesson concepts with spaced repetition.

Planning got estimation tools. Power estimation, area estimation per RTL construct, latency budgets, and risk assessment templates.

Full changelog

See releases.md for the complete list.

Install / Update

claude plugin marketplace add codejunkie99/Gateflow-Plugin
claude plugin install gateflow

GateFlow v2.3.0 — The Open-Source Hardware Platform

GateFlow v2.3.0 — The Open-Source Hardware Platform

AI-powered hardware development — design, verify, synthesize, and deploy working RTL with natural language.

18 agents · 18 commands · 26 skills · 8 IP blocks · 4 boards · 7 protocol references · 5 ecosystem integrations

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Highlights

Formal Verification from Natural Language

"Formally verify that the FIFO never overflows"
→ Generates SVA properties → Runs SymbiYosys → Reports proof or counterexample in English

IP Auto-Detection & Auto-Fill

/gf-detect --auto-fill
→ Scans codebase → Finds missing modules → Matches to verified IP → Implements with approval

Full Pipeline: Natural Language → Running Hardware

Describe → Plan → Build → Lint → Simulate → Formal → Synthesize → P&R → Pin Map → Flash

Board-Aware Pin Mapping

/gf-pinmap arty-a7-35t spi pmod-ja
→ Generates .xdc with correct PACKAGE_PIN, IOSTANDARD, DRIVE, SLEW

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What's New in v2.3.0

Quality Pass (28 files, +674 lines)

• Expanded 5 IP block READMEs from 2-line stubs to full documentation with instantiation examples
• Added complete port lists to 5 block.yaml files
• Added 4 missing protocol references (UART, Wishbone, AXI4-Full, AXI-Stream)
• Expanded Basys 3 constraints to all 16 LEDs, 16 switches, 7-segment display
• Expanded Tang Nano 9K constraints with UART and SPI flash pins
• Updated orchestrator routing table with all Phase 3-4 agents
• Updated /gf-doctor with tiered tool display

New Commands

• /gf-pcb — Generate KiCad schematic/PCB (AI-verified drafts)
• /gf-pinmap — Generate pin constraint files for target board
• /gf-cocotb — Generate Python testbenches using Cocotb
• /gf-fusesoc — Generate FuseSoC .core build files

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Complete Feature List

Agents (18)

Agent	Expertise
sv-codegen	RTL generation
sv-testbench	Testbench creation
sv-debug	Simulation debugging
sv-formal	Formal verification (SymbiYosys)
sv-synth	Yosys synthesis
sv-verification	SVA, coverage, formal
sv-understanding	Code analysis
sv-planner	Architecture planning
sv-orchestrator	Parallel builds
sv-refactor	Lint fixes, cleanup
sv-developer	Multi-file features
sv-tutor	Teaching, exercises
sv-viz	Terminal visualization
sv-pinmap	Pin assignment
sv-ip-scanner	IP detection & auto-fill
vhdl-codegen	VHDL generation
vhdl-testbench	VHDL testbenches
pcb-designer	KiCad schematic/PCB

Commands (18)

/gf-demo · /gf-lint · /gf-fix · /gf-sim · /gf-formal · /gf-gen · /gf-scan · /gf-map · /gf-doctor · /gf-ip · /gf-boards · /gf-detect · /gf-pnr · /gf-flash · /gf-pcb · /gf-pinmap · /gf-cocotb · /gf-fusesoc

IP Library (8 verified blocks)

Each includes RTL + self-checking testbench + SVA formal properties:

• fifo_sync · fifo_async · cdc_2ff · cdc_handshake · uart · spi_master · axi4lite_slave · debouncer

Board Database (4 boards)

With full constraint files (.xdc/.pcf/.cst):

• Digilent Arty A7-35T · Digilent Basys 3 · 1BitSquared iCEBreaker · Sipeed Tang Nano 9K

Protocol References (7)

• AXI4-Lite · AXI4-Full · AXI-Stream · SPI · I2C · UART · Wishbone

Ecosystem Integrations

• OpenClaw — ClawHub skill for autonomous hardware design
• F4PGA — Xilinx 7-series open-source synthesis
• OpenFPGA — Custom FPGA architectures (planned)
• OpenLane — ASIC tapeout SKY130/GF180 (planned)
• FuseSoC — Build system with Edalize backends

Platform Support

Claude Code (native) · OpenCode · Cursor · Cline · Windsurf · Codex CLI · Copilot CLI · OpenClaw

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Quick Start

# Install
claude plugin marketplace add codejunkie99/Gateflow-Plugin

# Try the demo
/gf-demo

# Or describe what you want
"Create an SPI controller for my Arty A7 and formally verify it"

Prerequisites

Tool	For	Install
Verilator	Lint + sim	brew install verilator
Yosys	Synthesis	brew install yosys
SymbiYosys	Formal	pip install symbiyosys
GHDL	VHDL	brew install ghdl
nextpnr	P&R	brew install nextpnr
openFPGALoader	Flash	brew install openfpgaloader
KiCad	PCB	brew install --cask kicad

All optional — GateFlow works in code-generation-only mode with zero tools installed.

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Built for hardware engineers who want to move faster.
Design. Verify. Ship.

GateFlow v2.2.1 — IP Auto-Detection & Auto-Fill

Patch release adding IP auto-detection and auto-fill capabilities.

New: /gf-detect — Scan & Fill IP Gaps

Scans your hardware codebase and automatically identifies:

• Missing modules — instantiated but never defined
• Stub modules — defined but empty (TODO markers)
• Standard IP patterns — ad-hoc FIFOs, CDC, UART, SPI, AXI that could use verified blocks
• CDC violations — clock domain crossings without synchronizers (CRITICAL)
• Vendor IP — primitives with open-source alternatives

Auto-Fill Mode

/gf-detect --auto-fill

Detects gaps → presents findings → user approves → agents implement.

Sub-Agent Capability

The sv-ip-scanner agent works as a skill other agents invoke mid-task. When sv-developer needs a FIFO, it can spawn sv-ip-scanner to check if one exists in the IP library before building from scratch.

Full release notes: See v2.2.0 release for complete feature list.

GateFlow v2.2.0 — The Open-Source Hardware Platform

GateFlow v2.2.0 — The Open-Source Hardware Platform

AI-powered hardware development — design, verify, synthesize, and deploy working RTL with natural language.

What's New

This release transforms GateFlow from an RTL assistant into a full-stack open-source hardware platform covering the entire development lifecycle.

Formal Verification from Natural Language ⚡

The killer feature. Describe what to prove in plain English:

"Formally verify that the FIFO never overflows and the pointers are always consistent"

GateFlow generates SVA properties, configures SymbiYosys, runs bounded model checking, and explains results — or counterexamples — in English.

Yosys Synthesis with Resource Reports

"Synthesize my design for the iCEBreaker"
→ LUTs: 142, FFs: 87, BRAM: 1, DSP: 0

Warns about unsupported SystemVerilog constructs before failing.

Drop-In IP Library (8 Verified Blocks)

Every block is lint-clean, simulation-tested, and formally verified:

• fifo_sync / fifo_async — Synchronous and async FIFOs
• cdc_2ff / cdc_handshake — Clock domain crossing primitives
• uart — TX+RX with configurable baud rate
• spi_master — All 4 CPOL/CPHA modes
• axi4lite_slave — AXI4-Lite register interface
• debouncer — Button debouncer with edge detection

Install with: /gf-ip add fifo_sync or "add a FIFO to my project"

Board-Aware Pin Mapping

Curated constraint files for 4 popular FPGA boards:

• Digilent Arty A7-35T (Xilinx)
• Digilent Basys 3 (Xilinx)
• 1BitSquared iCEBreaker (Lattice iCE40)
• Sipeed Tang Nano 9K (Gowin)

Query with /gf-boards arty-a7-35t or "what pins does the Arty A7 have?"

Multi-HDL Support

• SystemVerilog — Verilator, Icarus Verilog
• Verilog — Verilator, Icarus Verilog
• VHDL — GHDL (agents: vhdl-codegen, vhdl-testbench)

KiCad Schematic & PCB Generation

AI-verified draft designs with self-improving DRC/ERC/AI review loop. Confidence scoring and mandatory disclaimers on all outputs.

Full Pipeline

Natural Language → Plan → Build → Lint → Simulate
→ Formal Verify → Synthesize → Place & Route → Pin Map → Flash

Platform Support

Works across 7 AI coding platforms + OpenClaw:
Claude Code (native) | OpenCode | Cursor | Cline | Windsurf | Codex CLI | Copilot CLI | OpenClaw (ClawHub skill)

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By the Numbers

Component	Count
Agents	17
Commands	13
Skills	24
IP Blocks	8 (with real SystemVerilog)
Board Definitions	4
SystemVerilog Files	25
Protocol References	3 (AXI4-Lite, SPI, I2C)
Integrations	5 (OpenClaw, F4PGA, OpenFPGA, OpenLane, platforms)

New Components

Agents (+6)

• sv-formal — Formal verification (SVA + SymbiYosys)
• sv-synth — Yosys synthesis optimization
• sv-pinmap — Board-aware pin assignment
• vhdl-codegen — VHDL entity/architecture generation
• vhdl-testbench — VHDL testbenches (GHDL-compatible)
• pcb-designer — KiCad schematic/PCB with AI verification

Commands (+6)

• /gf-demo — Zero-config showcase project
• /gf-formal — Run formal verification
• /gf-ip — Manage IP block library
• /gf-boards — Query board pinouts
• /gf-pnr — Place & route with nextpnr
• /gf-flash — Flash FPGA via openFPGALoader

Skills (+12)

• gf-formal — Formal verification from natural language
• gf-synth — Yosys synthesis with resource reports
• gf-ip — IP block library manager
• gf-errors — 3-layer error translation (what/why/fix)
• gf-project — Project context (.gateflow/project.yaml)
• gf-pinmap — Board-aware pin mapping
• gf-pnr — nextpnr place & route
• gf-protocols — Protocol scaffolding (AXI4, SPI, I2C)
• gf-pcb — KiCad schematic/PCB generation
• gf-cocotb — Python testbenches via Cocotb
• gf-fusesoc — FuseSoC build system integration
• gf-learn-ctx — Contextual micro-lessons in workflows

---

Quick Start

# Install
claude plugin marketplace add codejunkie99/Gateflow-Plugin

# Try the demo
/gf-demo

# Or just describe what you want
"Create a FIFO and formally verify it never overflows"

Ecosystem Roadmap

Integration	Status
OpenClaw (ClawHub)	Ready
F4PGA (Xilinx open-source)	Ready
OpenFPGA (custom architectures)	Planned
OpenLane (ASIC tapeout)	Planned
Cocotb (Python verification)	Ready
FuseSoC (build system)	Ready

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Built for hardware engineers who want to move faster.
Design. Verify. Ship.

v1.5.3

What's Changed

Deterministic hooks — no more false blocks

• Replaced all prompt-based hooks with deterministic Python scripts — PostToolUse, UserPromptSubmit, and PreToolUse hooks now use fast, reliable scripts instead of LLM-based prompts
• Fixed PostToolUse hook blocking non-SV file writes (e.g. .ts, .json) — the prompt-based hook would hallucinate blocking messages; the new posttooluse-sv-lint-nudge.py script guarantees clean {} pass-through for non-SV files
• Made UserPromptSubmit hook nudge-only — never blocks non-SV prompts

Stop hook & stability

• Fixed Stop hook JSON output
• Defensive hook improvements

Docs

• Updated README formatting
• Added releases.md for version history

Full Changelog: v1.5.1...v1.5.3

v1.5.1 — Smart Hooks & README Overhaul

What's New

Smart Prompt-Based Hooks

GateFlow now watches your workflow and helps proactively with three new hooks:

• PreToolUse (Bash) — Warns before destructive commands that could delete or overwrite .sv/.v files (rm *.sv, git checkout -- *.sv, etc.)
• PostToolUse (Write|Edit) — Gentle lint reminder after editing SystemVerilog files
• Stop (Quality Gate) — Blocks session end if you modified SV files but forgot to lint or simulate. Passes through silently for non-SV work

All three use prompt-based hooks (LLM reasoning) instead of brittle regex matching — smarter and more context-aware.

README Restructure

• Cleaner flow: leads with natural language examples, features moved up
• Eliminated 3x redundant component listings → single Components section
• Collapsible <details> for Individual Downloads, Cross-Tool, and Troubleshooting
• Dynamic badges: GitHub stars + version pulled live from plugin.json
• Star History chart
• Updates changelog section

Deprecated

• userprompt-nudge.sh — replaced by prompt-based UserPromptSubmit hook (v1.5.0)
• stop-quality-gate.sh — replaced by prompt-based Stop hook

Old scripts moved to hooks/deprecated/ (gitignored).

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Full Changelog: v1.5.0...v1.5.1

v1.5.0 — Terminal Visualization

What's New

Terminal Visualization (/gf-viz + sv-viz)

Explore your RTL codebase visually in the terminal:

• Module hierarchy — ASCII tree of your design hierarchy
• FSM state diagrams — Unicode box-drawing state machines
• Module detail cards — Ports, parameters, always blocks at a glance

You: visualize the codebase
You: show the FSM in uart_tx
You: show module detail for fifo_sync

New Components

• gf-viz skill — auto-activates on "visualize", "show hierarchy", "show FSM"
• sv-viz agent — specialized terminal rendering agent

Other Changes

• Converted UserPromptSubmit hook from bash regex to prompt-based (fixes false positives)
• Root-level skills/ and agents/ symlinks for easier browsing
• Navigation docs for skills and agents directories

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Full Changelog: v1.4.4...v1.5.0

v1.4.4 — Individual Downloads & Cross-Tool Support

What's New

Individual Component Downloads

Don't need the full plugin? Grab just the skills, agents, or commands you want:

# Download a single agent
curl -O https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/agents/sv-codegen.md

# Download a skill
mkdir -p skills/gf-plan
curl -o skills/gf-plan/SKILL.md https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/skills/gf-plan/SKILL.md

Cross-Tool Compatibility

GateFlow components now work across AI coding tools:

Tool	Status
Claude Code	Native (full plugin)
OpenAI Codex CLI	SKILL.md compatible
Cursor	Append to .cursorrules
GitHub Copilot CLI	Append to .github/copilot-instructions.md
Cline	Append to .clinerules
Windsurf	Drop into .windsurf/rules/

Components Available

• 11 skills (orchestration, lint, sim, planning, learning, visualization)
• 10 agents (codegen, testbench, debug, verification, planning, refactor, etc.)
• 7 commands (lint, fix, sim, gen, scan, map, doctor)

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Full Changelog: v1.4.3...v1.4.4

v1.4.3 — Quality & Docs Improvements

What's New

Improvements

• Split gf-plan into modular reference files for better context management
• Validation fixes across skills and agents
• Improved documentation structure
• Orchestration reliability: result parsing, verification gates, retry tracking

Fixes

• Fix install docs and dependency checks
• Remove auto-install from SessionStart hook (now reports missing deps with manual guidance)
• Fix skill descriptions to use single-line YAML format

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Full Changelog: v1.2.0...v1.4.3