FPGA

Contents

Vitis는 Vivado WebPack(무료버전) 2020.2 에 포함되지 않는다. 2018.2 에는 예전 버전인 Xilinx SDK로 포함되어 있다.

Version Control

• https://www.fpgadeveloper.com/2014/08/version-control-for-vivado-projects.html/

My Projects

• https://github.com/stereoboy/Xilinx_Tutorials
• https://github.com/stereoboy/Advanced-Embedded-System-Design-Flow-on-Zynq
• https://github.com/stereoboy/High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS

Lectures & Blogs

Vivado workshop

• https://www.xilinx.com/support/university/vivado/vivado-workshops.html

XUP (Xilinx University Program)

• https://www.xilinx.com/support/university.html
  • Advanced Embedded System Design on Zynq using Vivado:
    • https://www.xilinx.com/support/university/vivado/vivado-workshops/Vivado-adv-embedded-design-zynq.html

Xilinx Wiki

• https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/394854562/Zynq-7000+Example+Designs

Others

• FPGA Developer

  • https://www.fpgadeveloper.com/

• "FPGA 강의"

  • https://blog.naver.com/PostView.nhn?blogId=ansdbtls4067&logNo=221238865180&parentCategoryNo=&categoryNo=&viewDate=&isShowPopularPosts=false&from=postView

• AI FPGA Blog, The Author is working on FPGA AI

  • https://blog.naver.com/chacagea/221745783425

• Verilog and ModelSim

  • https://youtube.com/playlist?list=PLieE0qnqO2kSZPQPMk8Vf1Rn_dAfRBs2-

• Xilnx SDK

  • Generating Basic Software Platform Reference Guide UG1138
    • https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug1138-generating-basic-software-platforms.pdf

• Xilinx Vivado Blogs

  • https://forums.xilinx.com/t5/Xcell-Daily-Blog-Archived/Introduction-to-the-Zynq-Triple-Timer-Counter-Part-One-Adam/ba-p/407537

• Xilinx Vivado Tutorials

  • IP Documents

    • https://www.xilinx.com/products/intellectual-property.html

  • Simulation Tutorial

    • https://www.xilinx.com/video/hardware/logic-simulation.html
    • zipped files:https://www.xilinx.com/support/documentation-navigation/see-all-versions.html?xlnxproducttypes=Design%20Tools&xlnxdocumentid=UG937
    • doc: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug937-vivado-design-suite-simulation-tutorial.pdf

  • Clock Wizard: https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v6_0/pg065-clk-wiz.pdf

  • IP Integrator, Block Ram Example

    

  • Vitis IDE for C/C++ Programming

    • How to Install Vitis: Step-by-Step

      

    • Xilinx Vivado Artix7 Fpga Microblaze Basic Design using Vivado 2019 CModA7 Vitis SDK

      

  • Getting started with Xilinx Vitis SDK and Vivado 2019.2 using Digilent Arty Z7 Zynq FPGA Arm

    • Use Block Diagram

      

  • ZYNQ for beginners: programming and connecting the PS and PL | Part 1

    

  • Vitis Unified Software Platform

    • https://www.xilinx.com/products/design-tools/vitis/vitis-platform.html

Verilog Tutorial

• http://classweb.ece.umd.edu/enee359a/verilog_tutorial.pdf

VHDL Tutorial

• https://course.ccs.neu.edu/cs3650/ssl/TEXT-CD/Content/Tutorials/VHDL/vhdl-tutorial.pdf
• https://www.ics.uci.edu/~jmoorkan/vhdlref/Synario%20VHDL%20Manual.pdf

Verilog2VHDL

• http://www.syncad.com/web_manual_bughunter_verilogger/bughunter_verilogger_main_index.html?v2vh_appendix.htm

HW

Xilinx

Zed Board

• https://www.fpgadeveloper.com/2014/03/comparison-of-zynq-boards.html/

Digilent Nexys A7

• https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/start
• Comments

  The only difference between the Nexys A7 and Nexys 4 DDR is the addition of the Nexys A7-50T variant of the Nexys A7, which has a smaller gate array. The Nexys A7-100T variant is functionally identical to the Nexys 4 DDR.

  • Nexys A7 Reference Manual (HW Spec Overview)
    • https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/reference-manual

Digilent Zybo Z7-20: Zynq-7000 ARM/FPGA SoC Development Board

• https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/start
  • Zybo Reference Manual
    • https://reference.digilentinc.com/reference/programmable-logic/zybo/reference-manual
• Buy
  • https://www.devicemart.co.kr/goods/view?no=1377333
  • https://www.devicemart.co.kr/goods/view?no=1383612

Blogs

• https://blog.naver.com/no1_devicemart/221895210415
• https://blog.naver.com/chacagea/221745783425

Digilent ZedBoard

• https://reference.digilentinc.com/reference/programmable-logic/zedboard/start

Memos

• Vitis Launch Failed

  https://forums.xilinx.com/t5/Vitis-Acceleration-SDAccel-SDSoC/Vitis-doesn-t-start/td-p/1074165

• Clock 관련

  • Reference: (온라인 워크숍 25강) [Verilog 강의 25강] STEP Motor Controller 1

    

  • 보드의 CLK 주파수는 고정된 값이다. 각 보드 업체의 Reference Guide의 Spec을 확인하자.

  • CLK 쪼개기 같은 함수를 Xilinx IP에서 제공한다. 이것은 C언어의 라이브러리 같은 기능인듯하다.

    • Clocking Wizard v6.0 LogiCORE IP Product Guide
      • https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v6_0/pg065-clk-wiz.pdf

  • Timing Report

    • Implementation(Left Menu Window) -> Floorplanning(Right Upper Corner)-> Timing Tab -> Design Timing Summary(Left Submenu Window) -> Setup/Hold Pulse Width
    • Negative Slack이 Minus 값을 갖는다면 문제가 발생한다

• Verilog Semantics

  • Register Shift

    reg [7:0] byte;
    wire tx;
    byte = {byte[6:0], tx};