3-bit ripple carry adder implemented using discrete NMOS transistors and NAND gate logic without using any digital ICs.
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Mar 5, 2026
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transistor-level-design
Here are 5 public repositories matching this topic...
Comparative analysis of transistor-level CMOS Full Adder architectures across 180nm, 90nm and 45nm technology nodes using Cadence Virtuoso with power and propagation delay evaluation.
asic eda vlsi semiconductor cadence-virtuoso cadence cmos low-power analog-design full-adder digital-vlsi transistor-level-design gpdk
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Jun 27, 2026
A practical day-by-day journey exploring Digital IC Design using Cadence Virtuoso — from schematics to layouts, DRC/LVS checks, parasitic extraction, and timing analysis.
schematic pex vlsi cadence-virtuoso vlsi-physical-design cmos digital-design custom-layout lvs ic-design drc learning-journal 45nm gdsii-flow post-layout-simulation eda-tools transistor-level-design
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Jul 30, 2025
A comprehensive ALU design project covering the full design cycle: from transistor-level schematic & simulation in LTspice to RTL modeling in Verilog.
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May 21, 2026 - Verilog
Cadence Virtuoso project of 5-stage ring oscillator
electronics vlsi electrical-engineering cadence-virtuoso cadence cmos ring-oscillator transistor-level-design
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Oct 23, 2025
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