Skip to content

Remove monkey patch#67

Open
jokap11 wants to merge 11 commits intotum-ei-eda:coredsl2from
jokap11:remove_monkey_patch
Open

Remove monkey patch#67
jokap11 wants to merge 11 commits intotum-ei-eda:coredsl2from
jokap11:remove_monkey_patch

Conversation

@jokap11
Copy link

@jokap11 jokap11 commented Mar 20, 2026

This is an initial commit and proof of concept aimed at replacing the current patch_model function with an ExprVisitor metaclass that supports overrideable (or optionally enforced) visitor aka generator functions.

The basic patch_model replacement consists of an own Subclass of the ExprVisitor with an own dispatched recursive generate function that differs its behavior regarding its input type (behav.{type}).
Therefore no global shared function set exists anymore. Also non existent generation overloads lead to
an NotImplemented exception -> Improvement of determinism

jokap11 added 9 commits March 21, 2026 11:27
Removed patch_model for ExprVisitor
1to1 mapping from xmnn-isax-flow/cdsl/top.core_desc to etiss
for pre patch_model to current flow
Caution: Most of the transform is generated by Copilot
1to1 mapping from xmnn-isax-flow/cdsl/top.core_desc to etiss
for pre patch_model to current flow
@jokap11
Copy link
Author

jokap11 commented Mar 21, 2026

Update I removed all patch_model() instances and have for an example core no difference in generated etiss code:

hans@jkamd:~/highlevelsynth/xmnn-isax-flow/cdsl$ diff -r gen_output gen_output_before_visitor/
diff -r gen_output/top/RV32IMACFDXCoreVXMNN/CMakeLists.txt gen_output_before_visitor/top/RV32IMACFDXCoreVXMNN/CMakeLists.txt
1c1
< # Generated on Sat, 21 Mar 2026 21:00:51 +0100.
---
> # Generated on Sat, 21 Mar 2026 10:30:30 +0100.
diff -r gen_output/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNNArch.cpp gen_output_before_visitor/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNNArch.cpp
2c2
<  * Generated on Sat, 21 Mar 2026 21:00:51 +0100.
---
>  * Generated on Sat, 21 Mar 2026 10:30:30 +0100.
diff -r gen_output/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNNArch.h gen_output_before_visitor/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNNArch.h
2c2
<  * Generated on Sat, 21 Mar 2026 21:00:51 +0100.
---
>  * Generated on Sat, 21 Mar 2026 10:30:30 +0100.
diff -r gen_output/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNNArchLib.cpp gen_output_before_visitor/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNNArchLib.cpp
2c2
<  * Generated on Sat, 21 Mar 2026 21:00:51 +0100.
---
>  * Generated on Sat, 21 Mar 2026 10:30:30 +0100.
diff -r gen_output/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNNArchSpecificImp.cpp gen_output_before_visitor/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNNArchSpecificImp.cpp
2c2
<  * Generated on Sat, 21 Mar 2026 21:00:51 +0100.
---
>  * Generated on Sat, 21 Mar 2026 10:30:30 +0100.
diff -r gen_output/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNNArchSpecificImp.h gen_output_before_visitor/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNNArchSpecificImp.h
2c2
<  * Generated on Sat, 21 Mar 2026 21:00:51 +0100.
---
>  * Generated on Sat, 21 Mar 2026 10:30:30 +0100.
diff -r gen_output/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNNFuncs.c gen_output_before_visitor/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNNFuncs.c
2c2
<  * Generated on Sat, 21 Mar 2026 21:00:51 +0100.
---
>  * Generated on Sat, 21 Mar 2026 10:30:30 +0100.
diff -r gen_output/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNNFuncs.h gen_output_before_visitor/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNNFuncs.h
2c2
<  * Generated on Sat, 21 Mar 2026 21:00:51 +0100.
---
>  * Generated on Sat, 21 Mar 2026 10:30:30 +0100.
diff -r gen_output/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNNGDBCore.h gen_output_before_visitor/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNNGDBCore.h
2c2
<  * Generated on Sat, 21 Mar 2026 21:00:51 +0100.
---
>  * Generated on Sat, 21 Mar 2026 10:30:30 +0100.
diff -r gen_output/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN.h gen_output_before_visitor/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN.h
2c2
<  * Generated on Sat, 21 Mar 2026 21:00:51 +0100.
---
>  * Generated on Sat, 21 Mar 2026 10:30:30 +0100.
diff -r gen_output/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNNInstr.cpp gen_output_before_visitor/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNNInstr.cpp
3c3
<  * Generated on Sat, 21 Mar 2026 21:00:51 +0100.
---
>  * Generated on Sat, 21 Mar 2026 10:30:30 +0100.
diff -r gen_output/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_RV32AInstr.cpp gen_output_before_visitor/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_RV32AInstr.cpp
3c3
<  * Generated on Sat, 21 Mar 2026 21:00:51 +0100.
---
>  * Generated on Sat, 21 Mar 2026 10:30:30 +0100.
diff -r gen_output/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_RV32DCInstr.cpp gen_output_before_visitor/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_RV32DCInstr.cpp
3c3
<  * Generated on Sat, 21 Mar 2026 21:00:51 +0100.
---
>  * Generated on Sat, 21 Mar 2026 10:30:30 +0100.
diff -r gen_output/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_RV32DInstr.cpp gen_output_before_visitor/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_RV32DInstr.cpp
3c3
<  * Generated on Sat, 21 Mar 2026 21:00:51 +0100.
---
>  * Generated on Sat, 21 Mar 2026 10:30:30 +0100.
diff -r gen_output/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_RV32FCInstr.cpp gen_output_before_visitor/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_RV32FCInstr.cpp
3c3
<  * Generated on Sat, 21 Mar 2026 21:00:51 +0100.
---
>  * Generated on Sat, 21 Mar 2026 10:30:30 +0100.
diff -r gen_output/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_RV32FInstr.cpp gen_output_before_visitor/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_RV32FInstr.cpp
3c3
<  * Generated on Sat, 21 Mar 2026 21:00:51 +0100.
---
>  * Generated on Sat, 21 Mar 2026 10:30:30 +0100.
diff -r gen_output/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_RV32ICInstr.cpp gen_output_before_visitor/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_RV32ICInstr.cpp
3c3
<  * Generated on Sat, 21 Mar 2026 21:00:51 +0100.
---
>  * Generated on Sat, 21 Mar 2026 10:30:30 +0100.
diff -r gen_output/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_RV32IInstr.cpp gen_output_before_visitor/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_RV32IInstr.cpp
3c3
<  * Generated on Sat, 21 Mar 2026 21:00:51 +0100.
---
>  * Generated on Sat, 21 Mar 2026 10:30:30 +0100.
diff -r gen_output/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_RV32MInstr.cpp gen_output_before_visitor/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_RV32MInstr.cpp
3c3
<  * Generated on Sat, 21 Mar 2026 21:00:51 +0100.
---
>  * Generated on Sat, 21 Mar 2026 10:30:30 +0100.
diff -r gen_output/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_tum_csrInstr.cpp gen_output_before_visitor/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_tum_csrInstr.cpp
3c3
<  * Generated on Sat, 21 Mar 2026 21:00:51 +0100.
---
>  * Generated on Sat, 21 Mar 2026 10:30:30 +0100.
diff -r gen_output/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_tum_retInstr.cpp gen_output_before_visitor/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_tum_retInstr.cpp
3c3
<  * Generated on Sat, 21 Mar 2026 21:00:51 +0100.
---
>  * Generated on Sat, 21 Mar 2026 10:30:30 +0100.
diff -r gen_output/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_tum_rvaInstr.cpp gen_output_before_visitor/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_tum_rvaInstr.cpp
3c3
<  * Generated on Sat, 21 Mar 2026 21:00:51 +0100.
---
>  * Generated on Sat, 21 Mar 2026 10:30:30 +0100.
diff -r gen_output/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_tum_semihostingInstr.cpp gen_output_before_visitor/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_tum_semihostingInstr.cpp
3c3
<  * Generated on Sat, 21 Mar 2026 21:00:51 +0100.
---
>  * Generated on Sat, 21 Mar 2026 10:30:30 +0100.
diff -r gen_output/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_XCoreVAluInstr.cpp gen_output_before_visitor/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_XCoreVAluInstr.cpp
3c3
<  * Generated on Sat, 21 Mar 2026 21:00:51 +0100.
---
>  * Generated on Sat, 21 Mar 2026 10:30:30 +0100.
diff -r gen_output/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_XCoreVBitmanipInstr.cpp gen_output_before_visitor/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_XCoreVBitmanipInstr.cpp
3c3
<  * Generated on Sat, 21 Mar 2026 21:00:51 +0100.
---
>  * Generated on Sat, 21 Mar 2026 10:30:30 +0100.
diff -r gen_output/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_XCoreVBranchImmediateInstr.cpp gen_output_before_visitor/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_XCoreVBranchImmediateInstr.cpp
3c3
<  * Generated on Sat, 21 Mar 2026 21:00:51 +0100.
---
>  * Generated on Sat, 21 Mar 2026 10:30:30 +0100.
diff -r gen_output/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_XCoreVMacInstr.cpp gen_output_before_visitor/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_XCoreVMacInstr.cpp
3c3
<  * Generated on Sat, 21 Mar 2026 21:00:51 +0100.
---
>  * Generated on Sat, 21 Mar 2026 10:30:30 +0100.
diff -r gen_output/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_XCoreVMemInstr.cpp gen_output_before_visitor/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_XCoreVMemInstr.cpp
3c3
<  * Generated on Sat, 21 Mar 2026 21:00:51 +0100.
---
>  * Generated on Sat, 21 Mar 2026 10:30:30 +0100.
diff -r gen_output/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_XCoreVSimdInstr.cpp gen_output_before_visitor/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_XCoreVSimdInstr.cpp
3c3
<  * Generated on Sat, 21 Mar 2026 21:00:51 +0100.
---
>  * Generated on Sat, 21 Mar 2026 10:30:30 +0100.
diff -r gen_output/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_XMNNInstr.cpp gen_output_before_visitor/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_XMNNInstr.cpp
3c3
<  * Generated on Sat, 21 Mar 2026 21:00:51 +0100.
---
>  * Generated on Sat, 21 Mar 2026 10:30:30 +0100.
diff -r gen_output/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_ZifenceiInstr.cpp gen_output_before_visitor/top/RV32IMACFDXCoreVXMNN/RV32IMACFDXCoreVXMNN_ZifenceiInstr.cpp
3c3
<  * Generated on Sat, 21 Mar 2026 21:00:51 +0100.
---
>  * Generated on Sat, 21 Mar 2026 10:30:30 +0100.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

1 participant